module port2RamDequeueCrossBar (
    input wire clk,
    input wire rst,
    input wire [15:0] dequeue_vld_port,                 //出栈使能
    input wire [5:0] dequeue_priority_port [0:15],
    input wire [15:0] dequeue_value [0:15],     //出队的旧队头
    output reg [15:0] set_channal_en,
    output reg [5:0] set_channal_value [0:15],
    output reg [15:0] dequeue_vld_ram,
    output reg  [9:0] dequeue_value_ram [0:15]
);
    wire [15:0] dequeue_vld_port1;
    wire [15:0] dequeue_vld_port2;
    wire [15:0] dequeue_vld_port3;
    wire [15:0] dequeue_vld_port4;
    wire [15:0] dequeue_vld_port5;
    wire [15:0] dequeue_vld_port6;
    wire [15:0] dequeue_vld_port7;
    wire [15:0] dequeue_vld_port8;
    wire [15:0] dequeue_vld_port9;
    wire [15:0] dequeue_vld_port10;
    wire [15:0] dequeue_vld_port11;
    wire [15:0] dequeue_vld_port12;
    wire [15:0] dequeue_vld_port13;
    wire [15:0] dequeue_vld_port14;
    wire [15:0] dequeue_vld_port15;
    wire [15:0] dequeue_vld_port16;
    wire [9:0] dequeue_value1 [0:15];
    wire [9:0] dequeue_value2 [0:15];
    wire [9:0] dequeue_value3 [0:15];
    wire [9:0] dequeue_value4 [0:15];
    wire [9:0] dequeue_value5 [0:15];
    wire [9:0] dequeue_value6 [0:15];
    wire [9:0] dequeue_value7 [0:15];
    wire [9:0] dequeue_value8 [0:15];
    wire [9:0] dequeue_value9 [0:15];
    wire [9:0] dequeue_value10 [0:15];
    wire [9:0] dequeue_value11 [0:15];
    wire [9:0] dequeue_value12 [0:15];
    wire [9:0] dequeue_value13 [0:15];
    wire [9:0] dequeue_value14 [0:15];
    wire [9:0] dequeue_value15 [0:15];
    wire [9:0] dequeue_value16 [0:15];
    wire [5:0] dequeue_priority_port1 [0:15];
    wire [5:0] dequeue_priority_port2 [0:15];
    wire [5:0] dequeue_priority_port3 [0:15];
    wire [5:0] dequeue_priority_port4 [0:15];
    wire [5:0] dequeue_priority_port5 [0:15];
    wire [5:0] dequeue_priority_port6 [0:15];
    wire [5:0] dequeue_priority_port7 [0:15];
    wire [5:0] dequeue_priority_port8 [0:15];
    wire [5:0] dequeue_priority_port9 [0:15];
    wire [5:0] dequeue_priority_port10 [0:15];
    wire [5:0] dequeue_priority_port11 [0:15];
    wire [5:0] dequeue_priority_port12 [0:15];
    wire [5:0] dequeue_priority_port13 [0:15];
    wire [5:0] dequeue_priority_port14 [0:15];
    wire [5:0] dequeue_priority_port15 [0:15];
    wire [5:0] dequeue_priority_port16 [0:15];

    reg [1:0] work_state [0:15];
    reg [15:0] history_dequeue_value [0:15];

    integer i;
    always @(posedge clk) begin
        if (rst) begin
            set_channal_en <= 16'h0000;
            for (i=0; i<16; i=i+1) begin
                set_channal_value[i] <= 0;
                work_state[i] <= 2'b00;
                history_dequeue_value[i] <= 0;
            end
        end
        else begin
            for (i=0; i<16; i=i+1) begin
                //输出通道选择信号
                if (work_state[i]==2'b00 && dequeue_vld_port[i]) begin
                    if (dequeue_value[i][15:10]>15) begin
                        work_state[i] <= 2'b01;
                        history_dequeue_value[i] <= dequeue_value[i];
                    end
                    //先给通道设置一个闭路，让它在出队期间不会传递别人的信号
                    set_channal_en[i] <= 1'b0;
                end

                if (work_state[i]==2'b01) begin
                    if (dequeue_vld_port[i]==0) begin
                        //出队完成，设置通道去传递对应RAM的数据
                        set_channal_en[i] <= 1'b1;
                        set_channal_value[i] <= history_dequeue_value[i][15:10]-16;
                        //状态转换
                        work_state[i] <= 2'b10;
                    end
                end

                if (work_state[i]==2'b10) begin
                    set_channal_en[i] <= 1'b0;
                    history_dequeue_value[i] <= 0;
                    //回到初始状态
                    work_state[i] <= 2'b00;
                end
            end
        end
    end

    dequeuePortDeMuxer16 part1Demux(.clk(clk), .rst(rst), 
                                    .dequeue_vld_in(dequeue_vld_port[0]),  .dequeue_value_in(dequeue_value[0]), .dequeue_priority_in(dequeue_priority_port[0]),
                                    .dequeue_vld_out(dequeue_vld_port1),  .dequeue_value_out(dequeue_value1), .dequeue_priority_out(dequeue_priority_port1));

    dequeuePortDeMuxer16 part2Demux(.clk(clk), .rst(rst), 
                                    .dequeue_vld_in(dequeue_vld_port[1]), .dequeue_value_in(dequeue_value[1]),  .dequeue_priority_in(dequeue_priority_port[1]),
                                    .dequeue_vld_out(dequeue_vld_port2), .dequeue_value_out(dequeue_value2), .dequeue_priority_out(dequeue_priority_port2));

    dequeuePortDeMuxer16 part3Demux(.clk(clk), .rst(rst), 
                                    .dequeue_vld_in(dequeue_vld_port[2]), .dequeue_value_in(dequeue_value[2]), .dequeue_priority_in(dequeue_priority_port[2]),
                                    .dequeue_vld_out(dequeue_vld_port3), .dequeue_value_out(dequeue_value3), .dequeue_priority_out(dequeue_priority_port3));

    dequeuePortDeMuxer16 part4Demux(.clk(clk), .rst(rst), 
                                    .dequeue_vld_in(dequeue_vld_port[3]), .dequeue_value_in(dequeue_value[3]), .dequeue_priority_in(dequeue_priority_port[3]), 
                                    .dequeue_vld_out(dequeue_vld_port4), .dequeue_value_out(dequeue_value4), .dequeue_priority_out(dequeue_priority_port4));
    
    dequeuePortDeMuxer16 part5Demux(.clk(clk), .rst(rst), 
                                    .dequeue_vld_in(dequeue_vld_port[4]), .dequeue_value_in(dequeue_value[4]), .dequeue_priority_in(dequeue_priority_port[4]), 
                                    .dequeue_vld_out(dequeue_vld_port5), .dequeue_value_out(dequeue_value5), .dequeue_priority_out(dequeue_priority_port5));

    dequeuePortDeMuxer16 part6Demux(.clk(clk), .rst(rst), 
                                    .dequeue_vld_in(dequeue_vld_port[5]), .dequeue_value_in(dequeue_value[5]), .dequeue_priority_in(dequeue_priority_port[5]),  
                                    .dequeue_vld_out(dequeue_vld_port6), .dequeue_value_out(dequeue_value6), .dequeue_priority_out(dequeue_priority_port6));

    dequeuePortDeMuxer16 part7Demux(.clk(clk), .rst(rst), 
                                    .dequeue_vld_in(dequeue_vld_port[6]), .dequeue_value_in(dequeue_value[6]), .dequeue_priority_in(dequeue_priority_port[6]),  
                                    .dequeue_vld_out(dequeue_vld_port7), .dequeue_value_out(dequeue_value7), .dequeue_priority_out(dequeue_priority_port7));

    dequeuePortDeMuxer16 part8Demux(.clk(clk), .rst(rst), 
                                    .dequeue_vld_in(dequeue_vld_port[7]), .dequeue_value_in(dequeue_value[7]), .dequeue_priority_in(dequeue_priority_port[7]), 
                                    .dequeue_vld_out(dequeue_vld_port8), .dequeue_value_out(dequeue_value8), .dequeue_priority_out(dequeue_priority_port8));

    dequeuePortDeMuxer16 part9Demux(.clk(clk), .rst(rst), 
                                    .dequeue_vld_in(dequeue_vld_port[8]), .dequeue_value_in(dequeue_value[8]), .dequeue_priority_in(dequeue_priority_port[8]), 
                                    .dequeue_vld_out(dequeue_vld_port9), .dequeue_value_out(dequeue_value9), .dequeue_priority_out(dequeue_priority_port9));

    dequeuePortDeMuxer16 part10Demux(.clk(clk), .rst(rst), 
                                    .dequeue_vld_in(dequeue_vld_port[9]), .dequeue_value_in(dequeue_value[9]), .dequeue_priority_in(dequeue_priority_port[9]),
                                    .dequeue_vld_out(dequeue_vld_port10), .dequeue_value_out(dequeue_value10), .dequeue_priority_out(dequeue_priority_port10));

    dequeuePortDeMuxer16 part11Demux(.clk(clk), .rst(rst), 
                                    .dequeue_vld_in(dequeue_vld_port[10]), .dequeue_value_in(dequeue_value[10]), .dequeue_priority_in(dequeue_priority_port[10]),
                                    .dequeue_vld_out(dequeue_vld_port11), .dequeue_value_out(dequeue_value11), .dequeue_priority_out(dequeue_priority_port11));

    dequeuePortDeMuxer16 part12Demux(.clk(clk), .rst(rst), 
                                    .dequeue_vld_in(dequeue_vld_port[11]), .dequeue_value_in(dequeue_value[11]), .dequeue_priority_in(dequeue_priority_port[11]),
                                    .dequeue_vld_out(dequeue_vld_port12), .dequeue_value_out(dequeue_value12), .dequeue_priority_out(dequeue_priority_port12));

    dequeuePortDeMuxer16 part13Demux(.clk(clk), .rst(rst), 
                                    .dequeue_vld_in(dequeue_vld_port[12]), .dequeue_value_in(dequeue_value[12]), .dequeue_priority_in(dequeue_priority_port[12]), 
                                    .dequeue_vld_out(dequeue_vld_port13), .dequeue_value_out(dequeue_value13), .dequeue_priority_out(dequeue_priority_port13));

    dequeuePortDeMuxer16 part14Demux(.clk(clk), .rst(rst), 
                                    .dequeue_vld_in(dequeue_vld_port[13]), .dequeue_value_in(dequeue_value[13]), .dequeue_priority_in(dequeue_priority_port[13]),
                                    .dequeue_vld_out(dequeue_vld_port14), .dequeue_value_out(dequeue_value14), .dequeue_priority_out(dequeue_priority_port14));


    dequeuePortDeMuxer16 part15Demux(.clk(clk), .rst(rst), 
                                    .dequeue_vld_in(dequeue_vld_port[14]), .dequeue_value_in(dequeue_value[14]), .dequeue_priority_in(dequeue_priority_port[14]),
                                    .dequeue_vld_out(dequeue_vld_port15), .dequeue_value_out(dequeue_value15), .dequeue_priority_out(dequeue_priority_port15));

    dequeuePortDeMuxer16 part16Demux(.clk(clk), .rst(rst), 
                                    .dequeue_vld_in(dequeue_vld_port[15]), .dequeue_value_in(dequeue_value[15]), .dequeue_priority_in(dequeue_priority_port[15]),
                                    .dequeue_vld_out(dequeue_vld_port16), .dequeue_value_out(dequeue_value16), .dequeue_priority_out(dequeue_priority_port16));

    genvar dmIndex;
    generate
        for (dmIndex=0; dmIndex<16; dmIndex=dmIndex+1) begin : dequeueMuxer
            dequeueMuxer16 denqueue(.clk(clk), .rst(rst), 
                                    .dequeue_vld_1(dequeue_vld_port1[dmIndex]), .dequeue_vld_2(dequeue_vld_port2[dmIndex]), .dequeue_vld_3(dequeue_vld_port3[dmIndex]), .dequeue_vld_4(dequeue_vld_port4[dmIndex]), .dequeue_vld_5(dequeue_vld_port5[dmIndex]), .dequeue_vld_6(dequeue_vld_port6[dmIndex]), .dequeue_vld_7(dequeue_vld_port7[dmIndex]), .dequeue_vld_8(dequeue_vld_port8[dmIndex]), .dequeue_vld_9(dequeue_vld_port9[dmIndex]), .dequeue_vld_10(dequeue_vld_port10[dmIndex]), .dequeue_vld_11(dequeue_vld_port11[dmIndex]), .dequeue_vld_12(dequeue_vld_port12[dmIndex]), .dequeue_vld_13(dequeue_vld_port13[dmIndex]), .dequeue_vld_14(dequeue_vld_port14[dmIndex]), .dequeue_vld_15(dequeue_vld_port15[dmIndex]), .dequeue_vld_16(dequeue_vld_port16[dmIndex]), 
                                    .dequeue_priority_1(dequeue_priority_port1[dmIndex]), .dequeue_priority_2(dequeue_priority_port2[dmIndex]), .dequeue_priority_3(dequeue_priority_port3[dmIndex]), .dequeue_priority_4(dequeue_priority_port4[dmIndex]), .dequeue_priority_5(dequeue_priority_port5[dmIndex]), .dequeue_priority_6(dequeue_priority_port6[dmIndex]), .dequeue_priority_7(dequeue_priority_port7[dmIndex]), .dequeue_priority_8(dequeue_priority_port8[dmIndex]), .dequeue_priority_9(dequeue_priority_port9[dmIndex]), .dequeue_priority_10(dequeue_priority_port10[dmIndex]), .dequeue_priority_11(dequeue_priority_port11[dmIndex]), .dequeue_priority_12(dequeue_priority_port12[dmIndex]), .dequeue_priority_13(dequeue_priority_port13[dmIndex]), .dequeue_priority_14(dequeue_priority_port14[dmIndex]), .dequeue_priority_15(dequeue_priority_port15[dmIndex]), .dequeue_priority_16(dequeue_priority_port16[dmIndex]), 
                                    .dequeue_value_1(dequeue_value1[dmIndex]), .dequeue_value_2(dequeue_value2[dmIndex]), .dequeue_value_3(dequeue_value3[dmIndex]), .dequeue_value_4(dequeue_value4[dmIndex]), .dequeue_value_5(dequeue_value5[dmIndex]), .dequeue_value_6(dequeue_value6[dmIndex]), .dequeue_value_7(dequeue_value7[dmIndex]), .dequeue_value_8(dequeue_value8[dmIndex]), .dequeue_value_9(dequeue_value9[dmIndex]), .dequeue_value_10(dequeue_value10[dmIndex]), .dequeue_value_11(dequeue_value11[dmIndex]), .dequeue_value_12(dequeue_value12[dmIndex]), .dequeue_value_13(dequeue_value13[dmIndex]), .dequeue_value_14(dequeue_value14[dmIndex]), .dequeue_value_15(dequeue_value15[dmIndex]), .dequeue_value_16(dequeue_value16[dmIndex]), 
                                    .dequeue_vld(dequeue_vld_ram[dmIndex]), .dequeue_value(dequeue_value_ram[dmIndex]));
        end
    endgenerate
endmodule